The present invention relates to a charge pump circuit.
In recent years, in nonvolatile memory devices called flash memories, reading/rewriting of data with a single supply voltage or low supply voltage is required, and a charge pump circuit which supplies a pumped voltage or negatively-pumped (pumped-down) voltage is necessary for performing each operation.
The specification of U.S. Pat. No. 5,422,586 (Patent Document 1) discloses a charge pump circuit wherein a charge pump operation is carried out with four clock signals having different phases to generate a pumped voltage. However, this charge pump circuit needs to have a sufficiently large clock margin for appropriately switching the four different clocks and has difficulty in increasing the clock frequency because of complicated clock control.
The specification of U.S. Pat. No. 4,214,174 (Patent Document 2) discloses a charge pump circuit wherein a charge pump operation is carried out with two clock signals having different phases to generate a pumped voltage. However, a transistor for transferring charge is a diode-connected transistor, which disadvantageously decreases the charge transfer efficiency.
With the intention to solve the above problems, IEEE_JOURNAL_OF_SOLID-STATE_CIRCUITS_VOL33_NO. 4_APRIL—1998 (Non-patent Document 1) discloses a charge pump circuit which will be described below.
FIG. 36 shows the structure of a charge pump circuit disclosed in Non-patent Document 1. The charge pump circuit 9 performs a charge pump operation with two clock signals CLK1 and CLK2 having different phases to generate pumped voltage Vpump. The charge pump circuit 9 includes pump cells 91, 92, 93, and 94, a subsidiary pump cell 95, and an anti-backflow circuit 96. The pump cells 91 and 93 (odd-numbered pump cells) receive clock signal CLK1, and the pump cells 92 and 94 (even-numbered pump cells) receive clock signal CLK2. The subsidiary pump cell 95 controls the trailing end pump cell 94. The anti-backflow circuit 96 prevents the backflow of charge.
The pump cells 91, 92, 93, and 94 each includes a charge transfer transistor 901, an off-switch transistor 902, an on-switch transistor 903, and a pump capacitor 904. The off-switch transistor 902 included in each of the pump cells 91, 92, 93, and 94 equalizes the input/output terminal N91, N92, N93 or N94 and the gate potential of the charge transfer transistor 901 such that the charge transfer transistor 901 is turned off. The on-switch transistor 903 turns on the charge transfer transistor 901. The pump capacitor 904 is pumped in synchronization with clock signal CLK1 (or CLK2). A subsidiary pump capacitor 905 is pumped in synchronization with clock signal CLK1 to turn on the charge transfer transistor 901 of the trailing end pump cell 94. A diode-connected transistor 906 transmits to the subsidiary pump capacitor 905 a voltage lower than the voltage of the input/output terminal N96 by a threshold voltage. A subsidiary input terminal N95 is connected to one end of the subsidiary pump capacitor 905 and also connected to the diode-connected transistor 906 and to the trailing end pump cell 94.
Next, the operation of the charge pump circuit shown in FIG. 36 is briefly described with reference to FIG. 37. First, at time T1, clock signal CLK1 transitions to HIGH level so that the voltages at the input/output terminals N92 and N94 and the subsidiary input terminal N95 are increased. Accordingly, in the pump cells 91 and 93, the off-switch transistor 902 becomes conducting, and the charge transfer transistor 901 becomes non-conducting. Meanwhile, clock signal CLK2 transitions to LOW level so that the voltages at the input/output terminals N93 and N96 are decreased. Accordingly, in the pump cells 92 and 94, the on-switch transistor 903 becomes conducting, and the charge transfer transistor 901 also becomes conducting. As a result, charge is transferred from the input/output terminal N92 to the input/output terminal N93 while charge is transferred from the input/output terminal N94 to the input/output terminal N96, so that the voltages at the input/output terminal N93 and the input/output terminal N96 increase.
Then, at time T2, clock signal CLK2 transitions to HIGH level so that the voltages at the input/output terminals N93 and N96 are increased. Accordingly, in the pump cells 92 and 94, the off-switch transistor 902 becomes conducting, and the charge transfer transistor 901 becomes non-conducting. Meanwhile, clock signal CLK1 transitions to LOW level so that the voltages at the input/output terminals N92 and N94 and the subsidiary input terminal N95 are decreased. Accordingly, in the pump cells 91 and 93, the on-switch transistor 903 becomes conducting, and the charge transfer transistor 901 also becomes conducting. As a result, charge is transferred from the input/output terminal N91 to the input/output terminal N92 while charge is transferred from the input/output terminal N93 to the input/output terminal N94, so that the voltages at the input/output terminal N92 and the input/output terminal N94 increase. The increase of the voltage at the input/output terminal N96 results in transfer of charge to the output of the pump cell 94 via the anti-backflow circuit 96, so that pumped voltage Vpump increases. Then, time T3, the same operation as that carried out at time T1 is performed.
In this charge pump circuit, the charge pump operation and charge transfer operation simultaneously occur in the pump cells 91 to 94 so that a long charge transfer duration can be secured. Also, clock signals are easily controlled. Further, the gate potential of the charge transfer transistor 901 which performs the charge transfer operation is controlled, whereby a decrease in charge transfer efficiency can be suppressed.
However, in the charge pump circuit disclosed in Non-patent Document 1, to control the charge transfer transistor of each pump cell to be conducting, the output voltage of the pump cell of the next circuit stage is used, and therefore, the difference in potential between terminals of the charge transfer transistor is large. For example, to render the charge transfer transistor non-conducting, the off-switch transistor is rendered conducting. Accordingly, the difference in potential between the gate and drain of the charge transfer transistor is “2·Vdd”. Thus, it is necessary to increase the breakdown voltage of the charge transfer transistor.
The charge pump circuit disclosed in Non-patent Document 1 can suppress the decrease in charge transfer efficiency in the pump cell as compared with the charge pump circuit of Patent Document 2 but uses a diode-connected transistor in the anti-backflow circuit at the trailing end circuit stage of the charge pump circuit, and therefore, the charge transfer efficiency disadvantageously decreases.